Exemplary Graduate Statement of Purpose

The first time I truly understood how unforgiving electronics can be was in an undergraduate lab, staring at a multistage amplifier that stubbornly refused to produce the expected gain. A classmate and I spent hours rechecking calculations and probing nodes, convinced we had missed something big. Eventually, we discovered the issue: a tiny bias mismatch in a single transistor that disrupted the behaviour of the entire circuit. Realizing that such a small deviation could destabilize an entire system fundamentally changed how I viewed electronics. It pushed me to look beyond just making circuits “work” and toward understanding how transistor-level choices ripple up into system-level performance. That mindset has guided my journey through projects, internships, and coursework, and it now motivates my pursuit of an M.S. in Electrical and Computer Engineering at Santa Clara University. One of the first times I applied this mindset at scale was in a project addressing the Von Neumann bottleneck that traditional 6T SRAM faces. I built and tested a 2×2 8T SRAM array, exploring how architectural and circuit-level changes could improve read–write robustness. I designed isolation circuits to separate read and write paths, enabling simultaneous operation without interference, and I implemented write drivers and sense amplifiers for reliable sensing at low voltage swings. Using Cadence Virtuoso for schematic design, I ran DC, transient, and corner simulations to validate stability across process, voltage, and temperature variations, iterating the design until it met noise margin and speed targets. This experience showed me how architecture, circuits, and device parameters intersect to determine the practical limits of memory performance. To deepen my understanding at the device level, my capstone project focused on designing differential amplifiers using FinFETs instead of conventional planar MOSFETs. I followed a full custom design flow: schematic capture and sizing in Cadence Virtuoso, model selection and bias point optimization, DC sweep and AC small-signal analysis to study gain and bandwidth, followed by transient simulations for slew rate and settling behaviour. I then moved to layout, carefully defining fin geometry and orientation, routing, and matching-critical devices, and ran DRC/LVS checks and parasitic extraction before performing post-layout simulations. Throughout this process, I developed an appreciation for how sensitive FinFET performance is to parameters such as fin height, fin width, gate oxide thickness, and channel length, and how those variations directly affect IV characteristics and overall amplifier behaviour. Quantitatively, the impact of these design choices was clear. Compared to a baseline MOSFET-based design, my FinFET differential amplifier achieved around a 25% increase in gain and roughly a 30% reduction in leakage power in simulation, along with improved noise performance. Through this project, I realized how even small innovations in transistor-level design can cascade into meaningful improvements at the circuit and system level—exactly the kind of leverage I want to explore further in graduate school. To complement this device- and circuit-level perspective with an understanding of real-world manufacturing, I interned in August 2024 in the SMT Production department at MNT Electronics, a PCB fabrication and assembly facility. There, I saw how theoretical designs confront the realities of solder paste, reflow profiles, and production throughput. I observed how issues like inadequate thermal relief, improper pad spacing, or poor component placement could lead to tombstoning, solder bridges, or intermittent connections after reflow. I also learned how design-for-manufacturability (DFM) considerations—such as consistent land patterns, proper stencil design, clear silkscreen, and realistic tolerances—directly impact yield, rework effort, and overall cost. This experience reinforced that good design is not just about elegant schematics; it is about robust, manufacturable systems that behave reliably on real hardware lines. My interest in VLSI and electronic systems, however, was not built solely on one memory project and one internship. It grew gradually as I repeatedly applied concepts from multiple courses, projects, and seminars. Lab-intensive classes in analog electronics, digital design, and microprocessors gave me a strong foundation in both transistor-level behavior and system-level architectures. Mini-projects—such as designing sensor interface circuits, experimenting with basic ADC/DAC-based data acquisition, and implementing simple controllers on microcontrollers—helped me see how the “ideal” circuits I studied in textbooks had to be adapted to noisy, imperfect real-world conditions. Additionally, certification courses outside my curriculum in IoT and embedded systems, along with seminars and workshops conducted at VIT, gave me the breadth I needed to appreciate the challenges of analog–digital interfacing and data reliability. Working with microcontrollers, communication protocols, and sensor networks exposed me to constraints such as limited power budgets, signal integrity over longer traces or cables, and the importance of robust sampling and filtering. Together, these experiences connected the dots between devices, circuits, boards, and systems, and they solidified my interest in pursuing integrated circuit and mixed-signal design more seriously. The M.S. in Electrical and Computer Engineering at Santa Clara University excites me because it offers exactly the kind of depth and rigor I need to grow in this direction. Courses in IC design, CMOS analog and digital circuits, and mixed-signal systems would allow me to systematically refine the intuitive understanding I have gained from projects into a solid theoretical and practical foundation. I am particularly drawn to the work of Dr. Shoba Krishnan on low-power SoCs, including techniques like resonant dynamic logic and the use of inductors for energy recovery, which align closely with my interest in energy-efficient, large-scale chip design. The research in nanoelectronics led by Professor Yang further demonstrates the breadth of Santa Clara’s expertise—from novel device structures to system-level applications—which I see as essential for the next generation of integrated systems. Ultimately, my goal is to become a design engineer capable of bridging transistor-level innovation with robust, manufacturable IC and SoC solutions for applications such as IoT edge devices and energy-efficient computing. The journey that began with a misbiased transistor in a simple amplifier has taken me through SRAM design, FinFET-based differential amplifiers, and SMT production lines, each step reinforcing the same lesson: small, well-informed design choices can transform the behaviour and impact of an entire system. At Santa Clara University, I want to sharpen my ability to make those choices—grounded in solid theory, validated through rigorous simulation and measurement, and informed by real-world constraints. I am eager to bring my hands-on experience in circuit design, my exposure to manufacturing, and my curiosity about device-level details to Santa Clara’s collaborative environment. In return, I hope to leave as an engineer capable of designing the kind of chips where a carefully tuned fin dimension or an efficiently recovered picojoule can make a measurable difference at scale. That is the kind of impact I want to have, and I believe Santa Clara University is the right place to help me achieve it.